Package: openocd-0.11.0 Version: 0.11.0-1 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 5738 Depends: libc6 (>= 2.38), libcapstone4 (>= 4), libftdi1-2 (>= 1.5), libgpiod2t64 (>= 1.1), libhidapi-hidraw0 (>= 0.8.0~rc1+git20140201.3a66d4e+dfsg), libjim0.82t64 (>= 0.73), libusb-0.1-4 (>= 2:0.1.12), libusb-1.0-0 (>= 2:1.0.16) Filename: amd64/openocd-0.11.0_0.11.0-1_amd64.deb Size: 2014884 MD5sum: fac63b5b04ae8a606b5fb2bb9c3b3fe3 SHA1: ba966234a37a628b984d6af1f6dec835fbbaf9b9 SHA256: 0406002797b1d5f61a592585afcebc403f4acfc3e8f37a6ce118595d389d9190 Section: embedded Priority: optional Homepage: http://openocd.sourceforge.net/ Description: Open on-chip JTAG/SWD debug solution for embedded target devices OpenOCD aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices. . The debugger uses an IEEE 1149-1 compliant JTAG TAP bus master to access on-chip debug functionality available on ARM based microcontrollers or system-on-chip solutions. For MIPS systems the EJTAG interface is supported. Additionally there is support for eSi-RISC, Intel, OpenRISC, RISC-V and ARC controllers. . User interaction is realized through a telnet command line interface, a gdb (the GNU debugger) remote protocol server, and a simplified RPC connection that can be used to interface with OpenOCD's Jim Tcl engine. . OpenOCD supports many different types of JTAG interfaces/programmers. Package: openocd-0.11.0-dbgsym Source: openocd-0.11.0 Version: 0.11.0-1 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 5032 Depends: openocd-0.11.0 (= 0.11.0-1) Filename: amd64/openocd-0.11.0-dbgsym_0.11.0-1_amd64.deb Size: 4755072 MD5sum: 9119f5eab235e09bce80df961ff612fc SHA1: ba75fb8da1db52adafbc027e8ea30c2e80608e8c SHA256: 521b0a2543ed82e399e953ed0d2483e031dd9e5b6b89420044cd771a4bef2aa3 Section: debug Priority: optional Description: debug symbols for openocd-0.11.0 Build-Ids: a2c8f2d20d3804bd24b522a569b84b5af6753790 Package: verilator-4.032 Version: 4.032-1 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 19878 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.032_4.032-1_amd64.deb Size: 4551900 MD5sum: ff7fccbecf2b030ff0948d6b0c30df0e SHA1: 9e0fbc295d8c8b43b6dececd91a19ab60ebc8691 SHA256: 0faf0fb15db28f659e212e5c519876948a6c9b1d92cace85b360cf74d1754338 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.032-dbgsym Source: verilator-4.032 Version: 4.032-1 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 93789 Depends: verilator-4.032 (= 4.032-1) Filename: amd64/verilator-4.032-dbgsym_4.032-1_amd64.deb Size: 89253684 MD5sum: d29c92f17d8674ea6d4e2dd247eee2e0 SHA1: a811c9d5a3158ca447ed7340049e089e09e12637 SHA256: 6384b8f347954a6f706c9a01e8e8a61385c7377025785b224751079d3d8cb6cd Section: debug Priority: optional Description: debug symbols for verilator-4.032 Build-Ids: 09012e646a521724daecad1947d40290515e74fa 33123a74e16036c817db97ff5dccccb572314192 e2d0009f86656741dee36e3300b71027bf2d9fc9 Package: verilator-4.034 Version: 4.034-1 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20397 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.034_4.034-1_amd64.deb Size: 4645428 MD5sum: 7da293ee17561a6491ea068db61951ef SHA1: a389a19ae97f0edafc43b6746b9e27e3c9253129 SHA256: b600619f2da9d3abb16cdc22d8604bd9310e5bb1d9b1e5a9c22d18551cd31dc4 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.034-dbgsym Source: verilator-4.034 Version: 4.034-1 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 96254 Depends: verilator-4.034 (= 4.034-1) Filename: amd64/verilator-4.034-dbgsym_4.034-1_amd64.deb Size: 91647116 MD5sum: 14ab0be931e944933ba401deff12e2e6 SHA1: ad523bf00e700828a2cdc7f187a995743b3be94f SHA256: d92cf1508144baeba141b7635b14811c9a5fdc78e87673b7477886ee9abae44f Section: debug Priority: optional Description: debug symbols for verilator-4.034 Build-Ids: 297f78d8366c3b971411250e473429a2d39035cd 3bef7add0065be1ced7fbf813d04100b031bc410 929aa9972c1b818374fc213b6895fb25005511a0 Package: verilator-4.040 Version: 4.040-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 21428 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.040_4.040-0_amd64.deb Size: 4910116 MD5sum: a49630be3784e177558bd80821d94107 SHA1: e789f66deb49ec2d54b83cab2024a194c3c1f572 SHA256: b35aca5b6d26b005b51f274e56aee4b8bb072845638304b6487f78553fd5041a Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.040-dbgsym Source: verilator-4.040 Version: 4.040-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 103108 Depends: verilator-4.040 (= 4.040-0) Filename: amd64/verilator-4.040-dbgsym_4.040-0_amd64.deb Size: 98474428 MD5sum: 8d7b38b86c99885d12d293e1fd14114e SHA1: 84c3ceff86807dc1c5ce1261979f613d90634f36 SHA256: a027aa25063eddb6d38821d18a2a572bb799358e7f613be6fad7fe0157d558e9 Section: debug Priority: optional Description: debug symbols for verilator-4.040 Build-Ids: aa978e84dbcdd8f5c4d2d7d2a06bb43941a81edb d00a46f85fff228fe24e16ad17de524a0336365a e686f8ef348fa1a8bad8a75b6db61f4886007dce Package: verilator-4.100 Version: 4.100-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 21810 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.100_4.100-0_amd64.deb Size: 5042148 MD5sum: 2a09d36c7d86668a5e494e2d176ed409 SHA1: 37ebdd05f73030e21f15ad2999dd08614d80e0d6 SHA256: 8918418acdcfd6c50c438db34f047c3fad940bdb732766458894743e9d32f3cd Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.100-dbgsym Source: verilator-4.100 Version: 4.100-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 107874 Depends: verilator-4.100 (= 4.100-0) Filename: amd64/verilator-4.100-dbgsym_4.100-0_amd64.deb Size: 103217876 MD5sum: 9161ecc1e271994a1e6bc06b52cbb6e2 SHA1: 64368580e2e6aee9301ebf14289e72597ea6206a SHA256: 6bbe047d0143e5c84c373b1580f6b9125f45d26de9f4a152e98c4f46c4a51c81 Section: debug Priority: optional Description: debug symbols for verilator-4.100 Build-Ids: 68bd96aab709b5bf5895dbc267d2317159257ef1 bcd7fd62534fc846dc1b3b4957cc5d7deb8e9346 bd474b591bd9a61f58d13c51611c79e716062160 Package: verilator-4.102 Version: 4.102-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 21788 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.102_4.102-0_amd64.deb Size: 5017140 MD5sum: 9b0d43c1581ce2d758bd429a646d79c0 SHA1: 5f15d9ee0e679e055ca8241b183280a6a36df0db SHA256: aa4bb2a9e0d835f6476358aa810c280cb98bedf1bb9f220f56f83c5f5de65863 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.102-dbgsym Source: verilator-4.102 Version: 4.102-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 107373 Depends: verilator-4.102 (= 4.102-0) Filename: amd64/verilator-4.102-dbgsym_4.102-0_amd64.deb Size: 102720440 MD5sum: a256e708528d83742514cb1b183572f1 SHA1: 237680fd46eff614298e142290512b1c7be81ce4 SHA256: 9a98298177bf46829319e8a107b6ccf4a20e48d26574d4e6a4e62097b3510ce9 Section: debug Priority: optional Description: debug symbols for verilator-4.102 Build-Ids: 3e51bab8588d29f3260aaaf00648cacad8d8c678 cb932a87638e378f21e15792ac24a27684772940 f859d90d7f5193116b316725258d6de4b218127b Package: verilator-4.104 Version: 4.104-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20322 Depends: libc6 (>= 2.29), perl, perl-doc Filename: amd64/verilator-4.104_4.104-0_amd64.deb Size: 4408228 MD5sum: 779eafdf157ac8bb70bbefcd735b888c SHA1: ea833cdbe03794a817433175695c93c1a7b6da07 SHA256: 9f3f9106d161923cb58b726aeffba98d391aeb8aefa5b2ab0d2232283e918638 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.104-dbgsym Source: verilator-4.104 Version: 4.104-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 102330 Depends: verilator-4.104 (= 4.104-0) Filename: amd64/verilator-4.104-dbgsym_4.104-0_amd64.deb Size: 100306748 MD5sum: 2b3ea6cd2ea3deecf8f894680172ac94 SHA1: 1335f006f8e3e7aac9030a78e7ef3ff9217ed2bd SHA256: f6714bae72bb1ea92e8915af9dffc758e983d69c39a3e578ea47315ba4d394c2 Section: debug Priority: optional Description: debug symbols for verilator-4.104 Build-Ids: 61cdf0b255dcc955bc44e0c4912d15fdcf11e84a 86703e7c786ab3e965062070ee26e7013bff5677 8cbf0e56cab49d7e5433279e9fd6efda50a90609 Package: verilator-4.106 Version: 4.106-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20416 Depends: libc6 (>= 2.29), perl, perl-doc Filename: amd64/verilator-4.106_4.106-0_amd64.deb Size: 4417856 MD5sum: 88b0494d3cb18532849bc6cdf655a111 SHA1: 7076825318d694aa7dda86ee3eb22c43fc7d087d SHA256: 32e32a724d6e900052791f97a98f1d815ffbdee0d8b11fbc05f35a0d4b29f782 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.106-dbgsym Source: verilator-4.106 Version: 4.106-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 103068 Depends: verilator-4.106 (= 4.106-0) Filename: amd64/verilator-4.106-dbgsym_4.106-0_amd64.deb Size: 101008296 MD5sum: d36f762bd5921596fc126b8411c2d7b5 SHA1: 58817e79686033d2282693c952baaef41e096f0d SHA256: 0e67f26b9e782d94d06850f56df73f975cd849a5ff0e684708ee1d15b2342379 Section: debug Priority: optional Description: debug symbols for verilator-4.106 Build-Ids: 16820fd8c7031453450c6e4e6481c61858d586e4 1d3461a93e7edb98bb4aaa70d243c21f19c29032 cb2c2b8209447c85ce0d240b735166dfa3782138 Package: verilator-4.108 Version: 4.108-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20630 Depends: libc6 (>= 2.29), perl, perl-doc Filename: amd64/verilator-4.108_4.108-0_amd64.deb Size: 4523440 MD5sum: 91f5dec8111bf721bae9172b80535ca6 SHA1: 4173b8133519a5b3079123e1f07ae6cddb43bd79 SHA256: cf1dfead6a1929e0fc41e6628ab6288a409ac86957532ed63647be01a069cf8c Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.108-dbgsym Source: verilator-4.108 Version: 4.108-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 104444 Depends: verilator-4.108 (= 4.108-0) Filename: amd64/verilator-4.108-dbgsym_4.108-0_amd64.deb Size: 102356652 MD5sum: 69c4e8f25d0d295ddabe0c5064702791 SHA1: 54e532c0b7839e39e6b83c041aaebcce66a9fb09 SHA256: 4a348a344922f7c2a41eb02f587decf43d0a347b38a3e98dc2fdf725a7a0ce3a Section: debug Priority: optional Description: debug symbols for verilator-4.108 Build-Ids: 0a71845dbeffd451e4267e68e5b6e94001cdd40a aa08307d793992d30ebb2c6021f7a301b2182f12 b96a9c3a9e5a76e4438b5a8d74b5b161d508c82a Package: verilator-4.110 Version: 4.110-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22438 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.110_4.110-0_amd64.deb Size: 5166864 MD5sum: 546a36f1b7aa7152702b849395e6e173 SHA1: 165e3ed6fed3ce88834f820f91b9ec21529c6006 SHA256: a63a2595dfc6dfb829d3f8daccbefdc1065bbe94522436b260155d374a5cec29 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.110-dbgsym Source: verilator-4.110 Version: 4.110-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 110890 Depends: verilator-4.110 (= 4.110-0) Filename: amd64/verilator-4.110-dbgsym_4.110-0_amd64.deb Size: 106138148 MD5sum: 1f77e5064db4341a952f69271d9015c8 SHA1: 55a2cc1ecd1bdec3b679b363cbbc77a3629558b6 SHA256: dc404a0638312e62fa3f9c6d42740f774ee68ebfcf08194c4938ec4cf9e4e738 Section: debug Priority: optional Description: debug symbols for verilator-4.110 Build-Ids: 36f62d0575f5ce6603d17c74525eb9c5be1b8808 6fd104bcd0472aa7d8e5e7b82f06751909f2acea b8fc312b71eb65a78c585a6799c87858d36d6f5c Package: verilator-4.200 Version: 4.200-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22476 Depends: libc6 (>= 2.38), perl, perl-doc Filename: amd64/verilator-4.200_4.200-0_amd64.deb Size: 5172416 MD5sum: d89bc763cfdc77840c8ca911066f4158 SHA1: 514d09a05ef013f6d542528c4454a00680723e94 SHA256: 0bd98c825c943ede3fa3c4d9c3acbf01a56f6fa1afa55c6521977c85d36854ec Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.200-dbgsym Source: verilator-4.200 Version: 4.200-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 110662 Depends: verilator-4.200 (= 4.200-0) Filename: amd64/verilator-4.200-dbgsym_4.200-0_amd64.deb Size: 105896184 MD5sum: 5ff03a1d7cf287c6ed74d9dc5b29d57f SHA1: 972fb26ca4561b5e06eab801b4e5163f46940c89 SHA256: f93fc49c86758d5c935324c2d46de958384e8ead6226edad0f4a45c5e8c5aae5 Section: debug Priority: optional Description: debug symbols for verilator-4.200 Build-Ids: 14f81c39a3f013008f70c814798a1bb777f049ba a1760258e51f47794c0d4f81cb3a4b8ebe916e9d bb623674d1cc757622345a27ea35fe5a5c6b68d6 Package: verilator-4.202 Version: 4.202-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 20844 Depends: libc6 (>= 2.33), perl, perl-doc Filename: amd64/verilator-4.202_4.202-0_amd64.deb Size: 4505760 MD5sum: 44b9a94630e04e15c6230ff477b9aefa SHA1: 4039852037ba40ffc0108ba362c510e6a56bd1d8 SHA256: 87399722ea9e0e53d1ca0b1b9e13389684c8921e857a1c1029d52d536f7452a0 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.202-dbgsym Source: verilator-4.202 Version: 4.202-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 104300 Depends: verilator-4.202 (= 4.202-0) Filename: amd64/verilator-4.202-dbgsym_4.202-0_amd64.deb Size: 103003528 MD5sum: 843cb2183b6b4eb552f6a440603d61c7 SHA1: 094017a80e113c54da01227ffaccdb54e003f92f SHA256: d850226867855c07d7c043fa5dccd42ffe23b3ba67bb2fa22388f03404476279 Section: debug Priority: optional Description: debug symbols for verilator-4.202 Build-Ids: 072308c5c3229203257ffb950d691430b70cfb8e 2363be2e94a73270f77a9cf1d9e5fee7711079cb f1075dc171c5d60699d47762b225c03edc6d7d00 Package: verilator-4.210 Version: 4.210-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22649 Depends: libc6 (>= 2.33), perl, perl-doc Filename: amd64/verilator-4.210_4.210-0_amd64.deb Size: 4628644 MD5sum: dac49879c3740f3418bc6b2c73c5df87 SHA1: 43e6490d1d751cc815c191b25d9b6f9fabf25424 SHA256: 3528a25c7448cd0587f3e500774010ca839cf14decd8cae7670d4294eb6593c2 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.210-dbgsym Source: verilator-4.210 Version: 4.210-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 111162 Depends: verilator-4.210 (= 4.210-0) Filename: amd64/verilator-4.210-dbgsym_4.210-0_amd64.deb Size: 109152212 MD5sum: b006614cb22c27d9971b1de27461d184 SHA1: 11c8790495fc6afd7dcdabf164f1d9a58952ea9e SHA256: 41d7a25ca42bd17c15f9b14b0463af5bfcd5c5352aaa0cac7e9d01199695bb57 Section: debug Priority: optional Description: debug symbols for verilator-4.210 Build-Ids: 4962b49bc23d30c07c1aef479e0a849bb6e2eeb0 7f017f23b6b1ff7bd47d47b895808b532149a8ab ef42827638c8358488735750d141f2b4da1658aa Package: verilator-4.212 Version: 4.212-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22922 Depends: libc6 (>= 2.33), perl, perl-doc Filename: amd64/verilator-4.212_4.212-0_amd64.deb Size: 4686672 MD5sum: 33f3962069e72a6bc807d52ac2e053b1 SHA1: bca1329e852185068ff7e5cc3ceb7a27efae2bc1 SHA256: 1daed6d0f821ad30464c5b10f478c56eaad122ecee29c9e6d4ea359e31b9b2da Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.212-dbgsym Source: verilator-4.212 Version: 4.212-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 114409 Depends: verilator-4.212 (= 4.212-0) Filename: amd64/verilator-4.212-dbgsym_4.212-0_amd64.deb Size: 112406048 MD5sum: bef88835df351c5aa415f8274d5b4381 SHA1: b2397af0ee6bfe7d3493555f5e26e2050b7e12dc SHA256: a91e2cc1dbff89138c22822234524ade622eae84d90ff1a5ecd04602a651f061 Section: debug Priority: optional Description: debug symbols for verilator-4.212 Build-Ids: 6c9af321c93026af834c971331c60f526c774076 b1e69798d75108d40e98583ce22ba9f68256141b e61aa1195ae742ba6823d408ac971a007e204828