Package: openocd-0.11.0 Version: 0.11.0-1 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 5738 Depends: libc6 (>= 2.38), libcapstone4 (>= 4), libftdi1-2 (>= 1.5), libgpiod2t64 (>= 1.1), libhidapi-hidraw0 (>= 0.8.0~rc1+git20140201.3a66d4e+dfsg), libjim0.82t64 (>= 0.73), libusb-0.1-4 (>= 2:0.1.12), libusb-1.0-0 (>= 2:1.0.16) Filename: amd64/openocd-0.11.0_0.11.0-1_amd64.deb Size: 2014884 MD5sum: fac63b5b04ae8a606b5fb2bb9c3b3fe3 SHA1: ba966234a37a628b984d6af1f6dec835fbbaf9b9 SHA256: 0406002797b1d5f61a592585afcebc403f4acfc3e8f37a6ce118595d389d9190 Section: embedded Priority: optional Homepage: http://openocd.sourceforge.net/ Description: Open on-chip JTAG/SWD debug solution for embedded target devices OpenOCD aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices. . 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It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.210-dbgsym Source: verilator-4.210 Version: 4.210-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 111162 Depends: verilator-4.210 (= 4.210-0) Filename: amd64/verilator-4.210-dbgsym_4.210-0_amd64.deb Size: 109152212 MD5sum: b006614cb22c27d9971b1de27461d184 SHA1: 11c8790495fc6afd7dcdabf164f1d9a58952ea9e SHA256: 41d7a25ca42bd17c15f9b14b0463af5bfcd5c5352aaa0cac7e9d01199695bb57 Section: debug Priority: optional Description: debug symbols for verilator-4.210 Build-Ids: 4962b49bc23d30c07c1aef479e0a849bb6e2eeb0 7f017f23b6b1ff7bd47d47b895808b532149a8ab ef42827638c8358488735750d141f2b4da1658aa Package: verilator-4.212 Version: 4.212-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 22922 Depends: libc6 (>= 2.33), perl, perl-doc Filename: amd64/verilator-4.212_4.212-0_amd64.deb Size: 4686672 MD5sum: 33f3962069e72a6bc807d52ac2e053b1 SHA1: bca1329e852185068ff7e5cc3ceb7a27efae2bc1 SHA256: 1daed6d0f821ad30464c5b10f478c56eaad122ecee29c9e6d4ea359e31b9b2da Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.212-dbgsym Source: verilator-4.212 Version: 4.212-0 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 114409 Depends: verilator-4.212 (= 4.212-0) Filename: amd64/verilator-4.212-dbgsym_4.212-0_amd64.deb Size: 112406048 MD5sum: bef88835df351c5aa415f8274d5b4381 SHA1: b2397af0ee6bfe7d3493555f5e26e2050b7e12dc SHA256: a91e2cc1dbff89138c22822234524ade622eae84d90ff1a5ecd04602a651f061 Section: debug Priority: optional Description: debug symbols for verilator-4.212 Build-Ids: 6c9af321c93026af834c971331c60f526c774076 b1e69798d75108d40e98583ce22ba9f68256141b e61aa1195ae742ba6823d408ac971a007e204828